基于I^2C总线的64×8Bits EEPROM芯片的设计与实现

Design of a 64×8Bits EEPROM Chip based on I^2C bus

本文主要阐述了一款基于I2C总线的64×8 Bits EEPROM芯片的设计与实现。首先介绍了I2C总线的特点及其工作原理。然后,对整个设计的框架,每个部分的功能做了说明。其中重点介绍了总线控制模块的设计与实现,并给出了该模块的主状态机。最后,对测试验证的方法,及验证结果做了介绍。

The design and implementation of a 64×8Bits EEPROM chip with an I^2C interface are described in this article. It firstly presents the protocol （its signals and how they work） of the I^2C bus. The architecture of the design and the function of each block are also described. It pays more attention on the block of I^2C bus protocol control and the state diagram of this block is also given. The design of the circuit has passed behavioral simulation and timing simulation after synthesis.