分数倍抽样率转换器的时变网络结构及其FPGA实现

Time-Varying Network Architecture of Fractional Multiple Sampling Rate Converter and Its FPGA Implementation

提出了分数倍抽样率转换器的高效时变网络结构的设计方法,并用现场可编程门阵列(FPGA)实现。通过对分数倍抽样率转换器的多相结构与时变网络结构的比较,指出在实现分数倍抽样率转换器时,时变网络结构克服了分数延迟的问题,结构简单;整个设计采用并行工作方式以提高系统的运算速度;采用低抽样率下进行滤波运算,从而大大降低了运算量。以I/D=256/1 023倍抽样率转换器为例,用FPGA XC 2V 250-5来实现时变网络结构的设计,芯片利用率为61%,最高工作频率可达92.225 MH z。

The design method for the efficient time-varying network architecture of the fractional multiple sampling rate converter is presented and its field programmable gate array （FPGA） is implemented. Compared the polyphase architecture with the time-varying network architecture of the fractional multiple sampling rate converter, the time-varying architecture overcomes a fractional delay problem when implementing the fractional multiple sampling rate converter, and so its structure is simple. This design for the parallel pipeline structure is used to improve the processing speed. The operated filtering at a low sampling rate can reduce the count quantity. When the fractional multiple sampling rate is I/D=256/1023, the whole design is implemented with one chip of XC2V250-5 FPGA, the use factor of the chip is 61% and the maximum frequency is 92. 225 MHz. The design is verified by simulation and measurement results.