一种在电路SOC验证接口设计方法研究

Research of One In Circuit SOC Verification Interface Design

SoC已经成为嵌入式系统设计中的关键器件,验证又是SoC设计的关键环节,占用SoC设计过程中60%以上的时间。专用测试设备及JTAG接口等主流SoC验证手段不便于SoC在系统联调时的验证。本文介绍了一种在电路SoC验证接口的设计方法,这种验证方法弥补了主流SoC验证方法在系统验证的不足,提高了SoC验证的效率。

SoC has been the key component in embedded system design, and the key step of SoC design is verification which engrosses more than 60 percents time during SoC design. Using definite purpose test equipment and JTAG interface ect which are main SoC verification means were deficiency when SoC in system couplet verification. We introduced one in circuit SoC verification interface design method, This verification method fetch up the deficiency of the main SoC verification method in SoC verification, and enhance the efficiency of SoC verification.