摘要
采用CSM C-H J 0.6μm CM O S工艺设计,可用于光纤通信系统中工作速率为622 M b/s的1∶4分接器。分析和设计了分接器的系统结构和单元电路,采用Sm artSp ice进行了仿真。整个电路采用5 V单电源供电,功耗为1.1 W。测试工作速率和各项技术指标达到相应标准。
A demultiplexer supposed to be employed in digital optic-fiber communication system was designed in CSMC-HJ CMOS technology. Its system construction and cell circuits were described. The simulation results demonstrated that this circuit can operate at a bit rate of 622 Mb/s with a power dissipation of 1.1 W under a 5 V supply.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
2005年第3期325-328,348,共5页
Research & Progress of SSE
基金
本课题受国家863计划项目863-SOC-Y-4-2资助
