并行钱氏搜索电路优化及高速RS译码器设计

An Optimized Parallel Chien's-searching Circuit and the Design of a High-speed RS Decoder

介绍用于光纤通信的速率为2.5 G b/s的高速RS(255,239)译码器设计。对输入信号中可能出现的超出译码器纠错能力的误码可进行检测判断,保证了误码不扩散。对译码器中大量使用的有限域乘法器进行了优化设计,尤其对并行钱氏搜索电路中的乘法器采用了按组优化设计方法,与直接实现方法相比,复杂度降低了45%。该RS译码器已用FPGA进行了功能验证,并用TSM C 0.18μm CM O S工艺实现,Synopsys综合后的仿真结果表明译码器电路时钟工作频率达到了330 MH z。

This paper presents the design of an RS（Reed-Solomon） decoder at a data rate of 2. 5 Gb/s with the ability of detecting uncorrectable message for optical communication systems. Parallel Chien＇s-searching circuit is used to reduce the output latency. The optimization of GF multipliers in parallel Chien＇-searching circuits reduced the hardware complexity by 45%, as compared to the direct implementation. The RS decoder has been functionally verified using FPGA and implemented by TSMC 0, 18μm CMOS standard cell. The simulation results of post-synthesis by Synopsys show that the RS decoder can run up to 330 MHz.