变参数RS译码器IP核的实现

IP Core Design for Varied Parameters RS Decoder

设计出一种码长可以变化的RS码译码器IP核电路,可进行RS(15,5)、RS(15,7)、RS(15,9)以及RS(15,11)的译码。译码器电路使用BM迭代译码算法,并在硬件电路中加以改进,使得电路能扩充到编译纠错位数多的复杂RS码。该译码器电路尽可能多地使用可以共享的模块,降低了电路的规模。硬件电路采用V erilogHDL进行描述,并在FPGA上进行了验证,同时给出了硬件电路在逻辑分析仪上得到的结果。

A variable RS decoder with IP core circuit is designed in this paper,and the circuit can decode RS（15,5）,RS（15,7）,RS（15,9） and RS（15,11）. BM iterative decode algorithm is availed in the decoder,and the circuit has been imporoved to decode complicated RS code. Moreover,there are many shareable modules used in the decoder,and it can reduce the circuit scale. The decoder is described by Verilog Hardware Description Language,and verified in FPGA. The paper shows the hardware verification result in logic analyzer.