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深亚微米CMOS模拟单元电路综合系统 被引量：1

Synthesis System of Deep-Sub-Micron Cell-Level CMOS Analog Circuit
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摘要 介绍了一个基于公式的深亚微米CMOS模拟单元电路综合系统.通过较准确地计算电路的直流工作点和MOS管的小信号参数,以及由电路拓扑结构自动生成电路性能公式对已有的基于公式的方法进行了改进;同时考虑了电路的可制造性问题,使得综合出的电路在工艺波动和工作条件变化时仍能满足性能要求.大量的实验结果表明:与基于模拟器的方法相比,采用该系统可以快速综合出可制造的深亚微米CMOS模拟单元电路. A synthesis system of equation-based deep sub-micron cell-level CMOS analog circuit is presented in the paper. In the system, the operating point of the circuit and the small signal parameters of MOS transistor are calculated more accurately, and the circuit performance equations are generated from its topology automatically in order to improve the equation-based method. At the same time, manufacturability is taken into account to make the synthesized circuit still meet specifications when parametric fluctuations in the manufacturing process and the variance in their operating conditions occur. It has been demonstrated that compared to simulator-based method, manufacturable deep sub-micron CMOS analog circuits can be synthesized using this system in a short run time.
作者 易婷 洪志良
机构地区 复旦大学微电子学系专用集成电路与系统国家重点实验室
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2005年第9期2046-2052,共7页 Journal of Computer-Aided Design & Computer Graphics
关键词 模拟电路综合 优化 集成电路CAD analog circuit synthesis optimization IC CAD
分类号 TN402 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献11

  • 1Nye W, Riley D C, Sangiovanni-Vincentelli A, et al. DELIGHT.SPICE: An optimization-based system for the design of integrated circuits [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988, 7(4): 501～519.
  • 2Koh H Y, Sequin C H, Gray P R. OPASYN: A compiler for CMOS operational amplifiers[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990, 9(2): 113～125.
  • 3Krasnicki M J, Phelps R, Hellums J R, et al. ASF: A practical simulation-based methodology for the synthesis of custom analog circuits[A]. In: Proceedings of IEEE/ACM International Conference on Computer Aided Design, San Jose, California, 2001. 350～357.
  • 4Ochotta E S, Rutenbar R A, Carley L R. Synthesis of high-performance analog circuits in ASTRX/OBLX[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1996, 15(3): 273～294.
  • 5Mukherjee T, Carley L R, Rutenbar R A. Efficient handling of operating range and manufacturing line variations in analog cell synthesis[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000, 19(8): 825～839.
  • 6Hagglund R, Hjalmarson E, Wanhammar L. A design path for optimization-based analog circuit design[A]. In: Proceedings of the 45th Midwest Symposium on Circuits and Systems, Tulsa Oklahoma, 2002, 1: 287～290.
  • 7Star-Hspice Manual[M]. Fremont, California: Avant! Corporation and Avant! Subsidiary, 1999.
  • 8BSIM3v3.2.2 MOSFET Model Users' Manual[M]. Berkeley, California: The Regents of the University of California, 1999.
  • 9易婷,洪志良.深亚微米CMOS运算放大器的综合[J].计算机辅助设计与图形学学报,2004,16(12):1631-1639. 被引量：8
  • 10李兴仁.[D].上海: 复旦大学,2000.

二级参考文献13

  • 1汪蕙，电子电路的计算机辅助分析与设计方法，1996年
  • 2李兴仁.[D].上海: 复旦大学,2000.
  • 3Nye W, Riley D C, Sangiovanni-Vincentelli A, et al. DELIGHT.SPICE: An optimization-based system for the design of integrated circuits[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988, 7(4): 501～519
  • 4Ochotta E S, Rutenbar R A, Carley L R. Synthesis of high-performance analog circuits in ASTRX/OBLX[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1996, 15(3): 273～294
  • 5Debyser G, Gielen G. Efficient analog circuit synthesis with simultaneous yield and robustness optimization[A]. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 1998. 308～311
  • 6Mukherjee T, Carley L R, Rutenbar R A. Efficient handling of operating range and manufacturing line variations in analog cell synthesis[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000, 19(8): 825～839
  • 7Degrauwe M G R, Nys O, Dijkstra E, et al. IDAC: An interactive design tool for analog CMOS circuits[J]. IEEE Journal of Solid-State Circuits, 1987, 22(6): 1106～1116
  • 8Koh H Y, Sequin C H, Gray P R. OPASYN: A compiler for CMOS operational amplifiers[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990, 9(2): 113～125
  • 9Krasnicki M J, Phelps R, Hellums J R, et al. ASF: A practical simulation-based methodology for the synthesis of custom analog circuits[A]. In: Proceedings of IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, 2001. 350～357
  • 10BSIM3v3.2.2 MOSFET Model Users' Manual[M]. Berkeley, CA: The Regents of the University of California, 1999

共引文献10

同被引文献11

  • 1C Toumazou,J B Huaghes,N C Battersby.开关电流一数字工艺的模拟技术[M].姚玉洁,等译.北京:高等教育出版社,1997:52-93.
  • 2V F Dias, V Liberali, F Maloberti. Design Tools for Oversampling Data Converters: Needs and Solutions [J]. Microelectronics Journal (S0026-2692), 1992, (23): 641-650.
  • 3Benabes P, Aldebert P, Kielbasa R. A Matlab Based Tool for Bandpass Continuous-time Sigma-Delta Modulators Design [C].Proceedings of the 1998 IEEE International Symposium on Circuits and Systems. Monterey CA: IEEE Press, 1998, 5: 274-277.
  • 4Chandra N, Roberts G W. Top-Down Analog Design Methodology Using Matlab and Simulink [C]. Proceedings of the 2001 IEEE International Symposium on Circuits and Systems. Sydney, Australia: IEEE Press, 2001, 5: 319-322.
  • 5Abel J. Behavioral Models of ASIC VLSI Cells [C].Proceedings of the Third Annual IEEE ASIC Seminar and Exhibit, New York: IEEE Press, 1990, 7: P12/1.1-P12/1.4.
  • 6Piero Malcovati, Simona Brigati, Fabrizio Francesconi, et al. Behavioral Modeling of Switched-Capacitor Sigma-Delta Modulators [J]. IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications (S 1057-7122). 2003.50(3): 352-364.
  • 7De la Rosa J M, Perez-Verdu B, Medeiro F, et al. Harmonic Distortion in Fully-Differential Switched-Current Sigma-Delta Modulators [C]. Proceedings of The Third Intamational Workshop on Design of Mixed-Mode Integrated Circuits and Applications, Vallarta, Mexico: IEEE Press 1999, 7: 134-137.
  • 8Yuan F, Youssef M, Yichuang Sun. Efficient Modeling and Analysis of Clock Feed-Through and Charge Injection of Switched Current Circuits [C].Proceedings of the Electrical and Computer Engineering, Canadian:IEEE Press, 2001, 5: 573-578.
  • 9Martins J, Dias V. Harmonic Distortion Due to Output Conductance in SI Cells [J]. Electronics Letters (S0013-5194). 1997, 33(2): 127-128.
  • 10Garcia M, Espinosa-F V G, Baez-Lopez D. Harmonic Distortion in Switched-Current Cells Due to Settling Error [C].Proceedings of The 9th IEEE International Conference on Electronics, Circuits and Systems, Dubrovnik, Croatia: IEEE Press, 2002, 9: 261-264.

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计算机辅助设计与图形学学报
2005年 第9期

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