一种降低DSP芯片总线功耗的设计方案

A Low Power Design of DSP Processor Bus

介绍了一种低功耗总线设计方案,在设计方案中提出了一种新的编码算法,并将其与一种低功耗译码器结合来降低总线的功耗。试验中选取了一些常用的DSP算法,结果证明这种方法可以有效降低DSP处理器中数据总线和地址总线的功耗,平均可达到对数据总线降低21.56%和对地址总线降低40.29%。

A novel low-power bus design for DSP processor is presented in the paper. The design integrates a new bus encoding for low-power and bus-Invert code. The design is proposed that significantly reduce transition activity on data and address buses. The experiments demonstrate significant reduction in transition activity of up to 21.56 % in data bus and up to 40. 29% in address bus.