HDTV SoC平台中的MPEG-2变长码解码芯片设计

Design of MPEG-2 Variable Length Decoder Chip for HDTV SoC Platform

提出了一种适用于高清晰度数字电视片上系统的MPEG-2变长码解码结构,采用MIPS4KcTM嵌入式CPU,在AM鄄BA总线的基础上设计了系统总线和系统的工作流程。根据MPEG-2视频码流的层次特点,模块间采用数据驱动结构,使用两级桶形移位寄存器实现并行解码结构,可缩短关键路径并简化控制逻辑。用硬件描述语言进行描述并通过逻辑功能仿真,用0.18μmCMOS工艺综合了变长码解码的RTL代码,时钟频率达到150MHz,并在XC6000型FPGA上通过验证。

A novel design of MPEG-2 variable length decoder for HDTV SoC platform is proposed. We design the system bus according to the AMBA specification, using the MIPS 4KcTM CPU as the embedded controller. According to the characteristic of MPEG-2 video data flow and its stratification, each processing unit is implemented with data driven architecture. Two stages of barrel shift registers are used so that each codeword can be processed in one clock period, shortening critical path and simplifying the logic of control. Timing and function simulation are performed. The RTL code of variable length decode is synthesized with 0.18μm CMOS technology. Finally, the design is tested by XC6000 FPGA.