摘要
高端路由器的IP层性能统计需要存储大量的数据,传统的方法用D触发器进行存储,往往消耗大量的逻辑单元和布线资源。文章给出一种用BlockRAM存储统计数据的设计方案,它有效利用FPGA内部的专用电路从而大量节省了逻辑和布线资源。该方案还具有良好的可扩展性。
IP layer performance statistics in high-end router require a large mount of local data storage, traditionally implementation with standard flip-flops, which can quickly consume many logic cells and routing resources. A more efficient alternative is to use BlockRAM, which saves logic cell and routing resources and provides a more efficient implementation with the dedicated circuitry. It can also provide good scalability.
出处
《计算机工程》
EI
CAS
CSCD
北大核心
2005年第18期221-222,225,共3页
Computer Engineering
基金
国家"863"计划信息技术领域重大专项课题(2001AA124011)