自采样比例积分控制全数字锁相环的性能分析和实现

THE IMPLEMENTATION AND ANALYSIS OF A SELF-SAMPLING PI CONTROL ALL DIGITAL PHASE-LOCKED LOOP

提出了一种基于自采样比例积分(PI)控制的全数字锁相环(ADPLL),并对该锁相环进行了详细的理论分析和仿真验证,最后用现场可编程逻辑器件(FPGA)予以实现。由于采用了自采样比例积分控制策略,使该锁相环在不同的锁频点具有几乎相同形式的传递函数,有利于理论分析和环路设计。理论分析、仿真验证和试验结果都表明该全数字锁相环具有环路参数设计简单、跟踪范围广、跟踪速度快、系统稳定性好、控制灵活等优点。该设计方案可以作为一个子系统或功能模块用来构成片上系统(SoC),用以提高控制系统的可靠性、简化系统的硬件结构。

A self-sampling PI （proportional-integral） control all digital phase-locked loop （ADPLL） is introduced in this paper. Our design is based on the self-sampling PI control scheme. An advantage of this is that the transfer function as linear approximation of the system model remains almost the same at different lock point, a feature enabling theoretical analysis and systematic design. The complete design procedure developed with Field programmable gate array （FPGA） devices and the detailed theoretical analysis are presented. Static, dynamic results of simulation and experiments are also presented, which show and verify that this ADPLL has good behaviors over wide tracking scope, fast tracking speed, excellent stability and flexible control characteristics. The ADPLL can act as a key part or a key module in a System on chip （SoC） digital system to simply the entire system＇s hardware architecture and ensure the high system reliability.