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一种基于进化规划的系统芯片测试调度方法 被引量:2

A Test Scheduling Method of SOC using Evolutionary Programming
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摘要 测试调度是系统芯片测试的一个重要方面,它用于确定把芯片上芯核的测试集分配给测试存取机制的方法,以使得总的测试时间最少。文章提出一种基于进化规划原理的测试调度方法,把测试调度问题的可行解用个体表示,由多个个体构成种群,通过种群的进化而得到较优的测试调度方案。 Test scheduling determines an assignment of cores to test access mechanism such that the overall test application time of system on chip (SOC) is minimized. A new test scheduling approach using evolutionary programming is presented in this paper, which uses individuals to represent the feasible solutions of test scheduling, the better scheduling scheme is obtained by the evolution of populations. The partition for the total width of test bus, as well as the assignment of cores to test access mechanism, can be obtained simultaneously. Experimental results show the approach can effectively solve test scheduling in reasonable time.
作者 陈翎 潘中良
出处 《广东自动化与信息工程》 2005年第3期1-3,共3页 Guangdong Automation & Information Engineering
基金 国家自然科学基金(60006002) 广东省教育厅自然科学然科研究项目(02109)资助
关键词 系统芯片 测试调度 嵌入核测试 进化规划 芯片测试 进化规划 调度方法 系统 测试调度 存取机制 测试时间 调度问题 调度方案 System on Chip Test Scheduling Embedded Core Testing Evolutionary Programming
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参考文献4

  • 1K.Chakrabarty.Test Scheduling for Core-Based Systems Using Mixed-Integer Linear Programming.IEEE Trans.CAD,2000,19(10):1163~1174
  • 2W.Zou,S.M.Reddy,I.Pomeranz,Y.Huang.SOC Test Scheduling Using Simulated Annealing.IEEE VLSI Test Symposium,2003:325~330
  • 3S.Koranne,V.Iyengar.On the Use of K-tuples for SOC Test Schedule Representation.Int.Test Conf,2002:539~547
  • 4C.Hyun.Cooperative mutation based evolutionary programming for continuous function optimization.Operations Research Letters.2002,30(3):195~201

同被引文献33

  • 1李莉,乔非,吴启迪.半导体制造重调度研究[J].中国机械工程,2006,17(6):612-616. 被引量:11
  • 2王然,吴澄.半导体制造中的车间层控制[J].信息与控制,1997,26(3):192-203. 被引量:6
  • 3崔晓英.SiC半导体材料和工艺的发展状况[J].电子产品可靠性与环境试验,2007,25(4):58-62. 被引量:8
  • 4半导体国际.IC封装市场在2007年将达到200亿美元.http://www.sichinamag.com/article/html 2003-8/20061121430452b6b1.htm.
  • 5CCID.芯片制造拉动中国集成电路产业快速成长[ED/OL].(2004-09-01)http://www.ceic.gov.cn/detail? record=1&channelid=44&presearchword=ID=135673&channelin=43.
  • 6BALASUBRAMANIAN H, MONCH L, FOWLER J, et al. Genetic algorithm based scheduling of parallel batch machines with incompatible job families to minimize total weighted tardiness[J]. Int J Production Research,2004,42(8) : 1 621-1 638.
  • 7UZSOY R, MARTIN-VEGA L A, LEE C Y,et al. Production scheduling algorithms for a semiconductor test facility[ J]. IEEE Trans on Semiconductor Manufacturing,1991,4(4) :270-280.
  • 8UZSOY R, LEE C Y, MARTIN-VEGA L A. Scheduling semiconductor test operations: minimizing maximum lateness and number of tardy jobs on a single machine [ J ]. Naval Research Logistics, 1992,39 (3) : 369-388.
  • 9GUPTA A K, SIVAKUMAR A I. Single machine scheduling with multiple objectives in semiconductor manufacturing [ J ]. The Inter J Advanced Manufacturing Technology, 2005,26 (9- 10) :950-958.
  • 10FREED T, LEACHMAN R C. Scheduling semiconductor device test operations on multihead testers[J]. IEEE Trans on Semiconductor Manufacturing, 1999,12(4) :523-530.

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