基于FPGA的比特并行DWDM光动态包交换系统

Bit-Parallel DWDM Optical Dynamic Packet Switching System Using FPGA

设计了一种全新的光路由器。采用单独的100 Mb/s的低速控制通道用来交换承载于波带(比特并行机制)带宽速率为80 Gb/s的包,这种基于现场可编程门阵列(FPGA)实现的机制使得宽带交换可以应用在具备低时延、低成本特点的本地网(LAN)中,商用化的FPGA用于驱动带宽的Mach-Zehnder干涉仪(MZI)和半导体光放大器(SOA)交换机。详细描述了为控制通道和数据通道设计的2种不同的时钟数据恢复模块(CDR)系统及其相关测试分析。对控制通道所有8个通道进行测试表明,在需要路由选址的情况下,测试结果稳定,且没有误码,和噪音层面出现。对于1 552.6 nm数据通道进行的背靠背和需要路由选址情况下,通过对MZI光交叉和SOA光交叉测量,得到额外的因为路由操作而导致的2.3 dB功率代价。

A novel router is demonstrated. Wavelength striped packets at 80 Gb/s aggregate bit rate are routed with a separate 100 Mb/s control channel for low cost LAN applications. A field programmable gate array（FPGA） drives the broadband MZl and SOA switches. The FPGA based scheme allows broadband switches for low latency and low cost local area networks（LAN） applications. Meanwhile,two different designs for the control data receiver（ODR） system for the control and data channels of a network have been developed with tests 干涉仪. Stable, error free operation is demonstrated for all eight channels for the control channels under routing operation with no evidence of noise floors. Measurements for back-to-back and routed performance for the 1 552.6 nm channel show an additional penalty due to routing operation of 2.3 dB for both MZ and SOA switches.