摘要
介绍一种采用多条运算流水线技术的粗粒度动态可重构计算系统,使得能够在时间维和空间维上同时开发算法的循环级并行性。在此基础上研究了可重构器件的组织结构形式以及面向动态可重构的互连网络,并给出了在该系统上求解一般问题(如FIR)的重构与执行过程。最后,为实现算法到结构的自动化映射而初步建立了协同编译器框架并展望了在系统中融合向量技术的前景。
In this paper, we present a coarse-grained run-time reconfigurable architecture that aims at exploiting loop level parallelism in both temporal and spatial dimensions by fitting multiple pipelines into the reconfigurable fabric. Basing on the system, we discuss the basic: cell and interconnection of the reconfigurable fabric. Also, we illustrate how the FIR is mapped onto and computed by our system. Finally, we present the supposed co-compiler framework and open up prospects for introducing vector processing to VPRS system.
出处
《微电子学与计算机》
CSCD
北大核心
2005年第10期88-91,95,共5页
Microelectronics & Computer
基金
国家自然科学基金资助项目(90307011)
关键词
可重构计算
流水线
算法映射
Reconfigurable computing, Pipeline, Algorithm mapping