一种低功耗常系数乘法器的设计

A Low Power Design of Constant Coefficient Multiplier

该文基于并行乘法器结构设计了一种新型的低功耗常系数乘法器。它采用了CSD(Canonical sign-digital)编码,W allace Tree乘法算法,结合采用了截断处理,变数校正的优化技术,实现了一种适用于DCT/IDCT变换的常系数乘法器。该乘法器的输入字长为15bits(Q3格式)输出字长为15bits(Q3格式),常系数字长为15bits(Q14格式)。采用SM IC0.18 um工艺进行综合,本设计的面积为13 974滋m 2,并在100M H z的时钟频率下功耗为0.69m w。通过与其它算法实现的乘法器进行分析与比较,说明了该设计在满足性能的同时,实现了较小的面积与较低的功耗。

In this paper a low power constant coefficient multiplier using CSD （Canonical sign-digital）coding Wallace Tree addition algorithm is presented.To reduce the area and power consumption of the multiplier,truncation and variable correction are adopted.For quantitative analysis the performance,the multipliers are synthesized in SMIC 0.18 um Technology.The proposed design has a measured power dissipation of 0.69mw and area of 13 974μm^2 at 100 MHz, which is better than other constant coefficient multipliers.