Verilog到VHDL翻译器的设计与实现

Design and implementation of translator of verilog to VHDL

描述了一个Verilog到VHDL翻译器Verilog2VHDL的设计与实现。首先将Verilog模块转换为中间格式,然后按照预定义的翻译规则,生成功能等价的VHDL设计实体。该翻译器目前只支持Verilog的一个子集。通过Verilog2VHDL,使得在Verilog-VHDL混合设计环境中重用Verilog设计成为可能。

The design and implementation of a translator from Verilog to VHDL were described. First, verilog modules to intermediate format, then according to the translating rules, equivalent VHDL entities in function were built. At present, this translator only support a subsets of verilog,