利用基地址相关的低功耗数据cache设计

Exploiting base address locality in low power data cache design

为了减少以地址偏移为主要寻址方式的精简指令处理器中数据cache的功耗,提出了充分利用读写指令相对于基地址的关联性,减少对cache的数据存储器和标志存储器的访问次数.通过建立两个数据结构来保存组选择信息:一个与通用寄存器一一对应的有效位表用来保证基地址仍然维持在原cache行;一个组选择信息表用来记录最近的cache访问的组选择信息,减少比较代价.该方法适用于多个组的组关联cache和可锁定的cache设计,已被应用于200 MHz的精简指令集(RISC)处理器中.该处理器采用TSMC0.18μm工艺,对一些基准程序进行了测试,结果显示该方法可以节省大约30%的数据cache功耗,还具有硬件代价小的优点.

To decrease the power of RISC processor data cache where load/store addressing modes dominated by displacement addressing mode and multiple-register mode, the novel method fully utilizes the locality information of base address in load/store instruction. A way-select table and a way-valid table are maintained to deselect certain ways of tag and data RAM in qualified situations. The method is applicable to set-associative cache with multiple ways, and is also applicable to lockable cache. This method was implemented in a 200 MHz high-performance low-power reduced instruction set computer （RISC） processor in a 0.18μm TSMC technology. The data cache power can be saved by about 30% with some well-known benchmark programs. While keeping the same performance, this method can be implemented with low hardware cost.