一种新型的抽取滤波器设计

Design of a Novel Decimation Filter

文章基于面积和功耗方面考虑提出了一种低功耗多相变级数非递归梳状滤波器结构,这种滤波器适合高阶过采样sigmadeltaA/D转换器。抽取滤波器采用Top-down方法设计,用0.6-μmCMOS标准单元实现,相比同样速度下的标准的非递归结构抽取滤波器节省了约1/3面积和功耗。

The paper presents a novel lower power polyphase transformable stage non-recursive comb filter architecture considering the area and power consumption,which is very suitable for high-order oversampling sigma delta A/D converters.The filter is designed by Top-down method and implemented using 0.6-μm CMOS standard cell.The proposed decimation filter has 1/3 less hardware area and power consumption compared to that of conventional non-recursive decimation filters at same circuit clock.