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High performance reconfigurable hardware system for real-time image processing

High performance reconfigurable hardware system for real-time image processing
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摘要 A novel reconfigurable hardware system which uses both muhi-DSP and FPGA to attain high performance and real-time image processing are presented. The system structure and working principle of mainly processing multi-BSP board, extended multi-DSP board are analysed. The outstanding advantage is that the communication among different board components of this system is supported by high speed link ports & serial ports for increasing the system performance and computational power. Then the implementation of embedded real-time operating systems (RTOS) by us is discussed in detail. In this system, we adopt two kinds of parallel structures controlled by RTOS for parallel processing of algorithms. The experimental results show that exploitive period of the system is short, and maintenance convenient. Thus it is suitable for real-time image processing and can get satisfactory effect of image recognition. A novel reconfigurable hardware system which uses both muhi-DSP and FPGA to attain high performance and real-time image processing are presented. The system structure and working principle of mainly processing multi-BSP board, extended multi-DSP board are analysed. The outstanding advantage is that the communication among different board components of this system is supported by high speed link ports & serial ports for increasing the system performance and computational power. Then the implementation of embedded real-time operating systems (RTOS) by us is discussed in detail. In this system, we adopt two kinds of parallel structures controlled by RTOS for parallel processing of algorithms. The experimental results show that exploitive period of the system is short, and maintenance convenient. Thus it is suitable for real-time image processing and can get satisfactory effect of image recognition.
出处 《Journal of Systems Engineering and Electronics》 SCIE EI CSCD 2005年第3期502-509,共8页 系统工程与电子技术(英文版)
基金 This project was supported by the National Natural Science Foundation of China(60135020) National Key Pre-researchProject of China(413010701 -3) .
关键词 MULTI-DSP fidd programmable gate arrays real-time image processing real time operating systems parallel structure. multi-DSP, fidd programmable gate arrays, real-time image processing, real time operating systems, parallel structure.
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