摘要
本文介绍了直接数字频率合成(DDS)的工作原理以及基于可编程片上系统(SOPC)实现DDS信号源。设计的DDS信号源以Cyclone器件为核心,用嵌入在FPGA中的N ios软核CPU作为控制来实现频率、相位和幅度的数字预制和步进,利用FPGA的RAM位放置正弦查找表,同时利用FPGA的逻辑单元实现相位累加等其它数字逻辑功能。实现了两路相位完全正交的DDS信号源。
The theory of DDS and the implementation of DDS based on SOPC are introduced,and DDS signal source is designed by using Cyclone apparatus as a core. The realization of the frequency, prefabricate and step move of the phase and amplitude is controlled by the Nios soft core CPU which is embeded in FPGA . The Sine look -up table is placed on FPGA＇s RAM, and the logistic unit of FPGA is used to realize phasic addition and other digital logic functions. The DDS signal source whose two phases are in quadrature is realized.
出处
《电讯技术》
2005年第5期69-71,共3页
Telecommunication Engineering
基金
2005年北京市教育委员会科技发展计划项目(KM200510009006)
关键词
可编程片上系统
直接数字频率合成
现场可编程门阵列
System on a Programmable Chip （SOPC）
Direct Digital Frequency Synthesis （DSS）
Field Programmable Gates Array （FPGA）
