摘要
提出了一种码率、约束长度可变Viterbi译码方案.译码器支持码率为1/2和1/3、约束长度3～7的卷积码,在FPGA上的综合及仿真结果表明其译码速率可达20 Mbps,与固定约束长度为7的译码方案相比,多占用的芯片资源不到8%.
A novel alterable parameter Viterbi decoder is presented, which supports constraint lengths from 3 to 7 and code rates 1/2 and 1/3. This decoder is synthesized on an FPGA. The results show that the overhead hardware resource associated with such a reconfigurable implementation as compared to a fixed constraint length 7 is no more than 8% , with a throughput of 20 Mbps.
出处
《电讯技术》
2005年第5期107-109,共3页
Telecommunication Engineering
