一种采用3级指令流水线的51内核设计

Design of 3stage Instruction Pipeline 51 Core

流水线技术是提高系统带宽的一项强大的实现技术,并且不需要大量附加的硬件设置。在微处理器设计中采用流水线技术是提高微处理器性能的一种很有效的方法。本文主要介绍了自行设计的一种采用3级指令流水线的51内核的设计和实现。内容包括:3级指令流水线的划分以及相应的系统结构框架,51指令集中各种类型指令的执行情况,间接寻址功能的实现方法,流水线数据相关问题的解决方案,最后讨论设计的FPGA实现。

Pipeline technology is a powerful implementation technology which can improve the systemrs bandwidth without many additional hardware components. It＇s an effective way to improve the microporcessor＇s performance by adopting pipeline technology. This paper is mainly about the design of 51 core, which adopts 3- stage instruction pipeline technology. First the compostion of the 3 -stage instruction pipeline and the inner structure of the 51 core are introduced. Then the paper focuses on the execution of all kinds of 8051 instructions. Also we discuss how to realize indirect addressing and the solution of the data dependence hazard. The last section of this paper is about the design realization by FPGA.