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Power Efficient Sub-Array in Reconfigurable VLSI Meshes

Power Efficient Sub-Array in Reconfigurable VLSI Meshes
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摘要 Given an m × n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. In this paper, new techniques are proposed, based on heuristic strategy, to minimize the number of switches required for the power efficient sub-array. Our algorithm shows that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing on the size of the sub-array. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques. Given an m × n mesh-connected VLSI array with some faulty elements, the reconfiguration problem is to find a maximum-sized fault-free sub-array under the row and column rerouting scheme. This problem has already been shown to be NP-complete. In this paper, new techniques are proposed, based on heuristic strategy, to minimize the number of switches required for the power efficient sub-array. Our algorithm shows that notable improvements in the reduction of the number of long interconnects could be realized in linear time and without sacrificing on the size of the sub-array. Simulations based on several random and clustered fault scenarios clearly reveal the superiority of the proposed techniques.
出处 《Journal of Computer Science & Technology》 SCIE EI CSCD 2005年第5期647-653,共7页 计算机科学技术学报(英文版)
关键词 degradable VLSI mesh RECONFIGURATION heuristic algorithm FAULT-TOLERANCE NP-COMPLETE degradable VLSI mesh, reconfiguration, heuristic algorithm, fault-tolerance, NP-complete
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参考文献14

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