ASIC设计中的静态时序分析技术

The Static Time Analysis Technology in ASIC Design

随着工艺线宽的减小,时序问题开始主导集成电路设计。为了解决全芯片的互连延时,需要全芯片分析和优化。PrimeTime 是Synopsys 公司全芯片和门级静态时序分析工具。PrimeTime 用来分析大型同步数字专用集成电路。静态时序分析是一种彻底的分析、调试、验证设计的方法。

As process geometries shrink, timing issues dominate IC design.In order to account for interconnect delays across the chip, we require full-chip analysis and optimization capability.PrimeTime is the Synopsys full chip and gate-level static timing analyzer.It analyzes the timing of large synchronous digital ASICs.Static timing analysis is an exhaustive method of analyzing, debugging and validating design oerformance.