摘要
研究了8B/10B编码的编码特点和内在相关性,并在此基础上介绍了一种用VerilogHDL设计8B/10B编解码逻辑描述的方法,将其嵌入到FPGA中或设计成ASIC,可构成一个资源使用少、速度快、可靠性高的IP核。文中着重介绍8B/10B编解码总体设计方案,详细描述其内部工作原理和实现。最后给出在Altera公司软件平台QuartusII上进行EDA的综合和仿真结果。
Based on logic analysis, inherent relationship between of 8B/10B code and the encode decoding method using Verilog HDL is investigated. With optimized logic gates, this method can be applied easily and effectively to high speed and low-power consumption FPGA design and ASIC design. In addition to its interwork elements and realization, this design highlighted the general function of 8B/10B encoder and decoder. Finally, synthesis and simulative result based on Quartus Ⅱ IDE of Ahera company are given.
出处
《国外电子元器件》
2005年第11期19-22,共4页
International Electronic Elements
