VLSI性能驱动工艺映射算法

A PERFORMANCE-DRIVEN TECHNOLOGY MAPPING ALGORITHM

在ＶＬＳＩ工艺映射过程中计算连线延时是非常困难的，因为此时未进行布图设计，不知道连线长度，本文提出一种称为布图算法驱动的工艺映射技术，其基本思想是研究面向映射的延时驱动布图算法，并用其进行工艺映射过程中的导线延时估计．

Calculating wire delay during mapping is very difficult because the wirelength can not be obtained before layout. This paper presents a new technique calledlayout algorithm driven technology mapping. The idea is to develop a timing drivenand mapping oriented layout algorithm, and estimate wire delay during the mappingbased on the layout algorithm.