摘要
该文介绍了电子计数法及其基本工作原理,结合电子计数法的优越性将之应用于雷达对抗中可以达到提取雷达脉冲重复间隔的目的。为了满足雷达脉冲重复间隔提取实时性的要求,该方法可以采用FPGA加以实现。根据FPGA开发流程,给出了雷达脉冲重复间隔测量的实现方案,最后使用FPGA开发软件QuartusⅡ4.0,选择VHDL语言作为设计输入进行计算机仿真,仿真结果有效验证了该方法的可行性与实现方案的有效性。
Electronic counter and its basic operation principle are introduced firstly in this paper. Making use of the advantages of electronic counter to radar countermeasure, radar pulse repeatition interval can be distilled. For the need of real - time distillation, this method can be realized by FPGA. Then, the project of radar PRI's measurement is presented based on FPGA exploitation flow. Lastly, Quartus Ⅱ 4.0, FPGA design software, is used and VHDL is chosen as design input for computer simulation. Simulation result validates the method's feasibility and the project's validity efficiently.
出处
《计算机仿真》
CSCD
2005年第10期26-30,共5页
Computer Simulation
关键词
电子计数
脉冲重复间隔
设计输入
元件
Electronic counter
Pulse repeatitioin interval
Design input
Component