薄膜全耗尽SOI门阵列电路设计与实现

Design and Development of TFD SOI Gate Array

在Ｄａｉｓｙ系统上设计出通用性强、使用方便的ＳＯＩ门阵列母版及门阵列电路，并采用１．５μｍＣＭＯＳ／ＳＯＩ工艺在薄膜全耗尽ＳＩＭＯＸ材料上得以实现，其中包括多种分频器电路和环形振荡器，环振可工作在２．５Ｖ，门延迟时间在５Ｖ时为４３０ｐｓ。

SOI gate array is designed in Daisy Design System and developed on thin film fully depleted SIMOX materials in 1.5μm CMOS/SOI technology.Some frequency dividers and ring oscillators are built on it.The propagation delay time is 430ps.We find that the gate array can work perfectly at Vdd=2.5V.