降低流水线型模数转换器功耗

A Method to Reduce Power Consumption in Pipelined A/D Converter

文中提出基于开关电容电路设计形式的功耗优化方法。该方法通过减小采样电容与反馈电容的比值来优化功耗,适用于高速、低精度的流水线型模数转换器。使用此方法可使每级位数均为1.5bit的流水线型模数转换器节省10％的功耗。

In this paper, a method of power optimization based on form of design of switch-capacitance circuit is proposed. The method optimizes power consumption by reducing the ratio of sampling capacitance to feedback capacitance and is applicable in high-speed low-resolution pipelined analog-to-digital converter. 1.5 bit/stage pipelined ADC dissipates 10% less power by using the method.