摘要
文章介绍改进的快速浮点加法器的设计方案。通过增加一个解码器和一些简单的逻辑实现了对IEEE非规格化数的支持。
In this paper we present an modified high-speed floating-point adder design. The adder accepts both normalized and denormalized number by adding a decoder and some simple logic units.
出处
《电子测量技术》
2005年第5期71-72,共2页
Electronic Measurement Technology
