一种全硬件动态指令翻译模型

A Hardware Oriented Model for Dynamic Instruction Translation

文章在研究分析DAISY和Cruseo(tm)这两款处理器后,针对X86指令集系统提出一种全硬件的动态翻译模型。该模型用RISC内核实现X86操作,指令翻译和转换完全用硬件实现。对于X86指令长度不定,取指部件效率不高,该模型使用多队列取指;RISC内核的执行采用路径预测技术。它的优点是在兼容的基础上尽可能地提高处理器性能。

Based on the study and analysis of the DAISY and the Crusoe （tm）, a hardware oriented model for dynamic instruction translation is proposed. It enables the RISC core to function as the X86 processor, and instruction translation and conversion is fully implemented by hardware. In view of inefficiency instruction fetching due to instruction length diversity, multiple instruction fetching is adopted, and the RISC core execution is based on trace prediction. It can improve the performance as possible while be compatible with the target.