基于FPGA乘法器架构的RNS与有符号二进制量转换

RNS to Binary Signed Conversion Based Multiplier on FPGA Architecture

RNS(余数数制系统)是一种整数运算系统,在粒度精确性,能源损耗和响应速度上有很大的优势。从RNS到二进制数的输入输出转换是基于余数算法的专用架构实现的关键。本文提出了一个基于N类模的RNS与有符号二进制量的通用转换算法在FPGAs的乘法器上的实现过程。该算法能更有效地进行有符号数与RNS的转换。基于该算法类型乘法器在同类型乘法器中显示出了速度优势。文章中该架构被映射到Altera的10K系列的FPGA上。

RNS （Residue Number System）is a kind of integer operation system, and it allows interesting advantages in terms of precision, power consumption and speed. Generally, the output conversion from residue to binary is the crucial point in effective realizations of application specific architectures based on residual arithmetic. This paper presents a general conversion procedure based a N moduli set on FPGAs multiplier. The algorithm can process both unsigned and signed numbers. This multiplier is the fastest in the following comparions.