一种新型面积优化的二维IDCT处理器

A New Cost Efficient pipeline 2-D IDCT Processor

本文提出了一种基于行列分解算法的8×8二维反向离散余弦变换(IDCT)处理器。不再需要传统的为保持输入列向量的输入寄存器和并串转换寄存器,这既减小了芯片面积又减小了处理延时。其中的一维离散余弦变换采用查找表实现,作为查找表的ROM比传统的分布式算法的ROM也小的多。我们提出的二维IDCT处理器不仅具有面积优化、低延时、高吞吐率的特点,并且具有规整的、全流水结构,因此非常适合VLSI和FPGA实现。

In this paper, a new cost efficient and high throughput 8 × 8 2 - D Inverse Discrete Cosine Transform （IDCT） processor is presented based on row- column decomposition structure. The 1 -D IDCT is based on the lookup table. The design does not require the input registers and parallel to serial shift registers to hold the input column data, so the latency is short. The ROM is very smaller than the conventional memory - based distributed algorithm in this design. The design is regular, full pipeline and is very suitable for the VLSI implementationl.