摘要
简要分析了CRC算法的基本原理。在传统串行CRC的实现基础上,介绍了一种快速的CRC并行算法,导出了32位并行CRC码的逻辑关系,推导过程简单。与查表法比较,此并行算法不需要存储大量的余数表,可以减少延迟。同时,这种并行处理方法也适合于其他位宽并行CRC码。最后,利用ISE开发平台和V erilog HDL硬件描述语言进行设计,实现了基于此并行算法的32位并行CRC 32码的编码器,并给出了仿真和综合结果。设计出来的CRC编码器,已经成功应用于以太网的接入系统中。
After having analyzed the principle of CRC calculation,this article introduces a fast parallel CRC calculation based on serial realization. This parallel calculation could easy deduce the logical relationship for 32 b parallel CRC. Comparing with Table Lookup Algorithm,it needn＇t store the large remainder table,and decrease the delay. This parallel processing method is also fit for other bit -wide CRC. Finally,using ISE platform and Verilog HDL,we have designed the 32 b CRC -32 encoder based on this parallel calculation,its simulation and synthesis results are provided, The designed encode have been successfully used to the Ethernet system.
出处
《现代电子技术》
2005年第22期21-23,26,共4页
Modern Electronics Technique
