基于EDA技术的高速FIFO设计

Designing of High Speed FIFO Base on EDA Technology

利用Lattice公司的在系统可编程逻辑器件ispLSI6192芯片构造4个双向、独立的128×9位F IFO高速数据存储栈区(FIFO),并对芯片可编程逻辑编程建立快速地址加1计数器以及FIFO控制逻辑,控制逻辑分别对4个FIFO栈区进行读/写控制;实现将系统的高速数据栈区及其控制逻辑功能在同一个芯片上实现,从而提高计算机数据通信的速度、效率以及提高系统的集成度和降低系统的故障率。

Application ispLSI6192 Device to make four bi-directional high speed data memory（FIFO） of 128 X 9 bit ;We can make address counter and address register base on high-speed adding logic of the device ,and make controlling logic base on programmable gate array and programmable register array;Controlling logic manage and control reading or writing operation of FIFO1-4 data memory;And because system＇s high speed data memory and it＇s controlling logic are in same device,so we can improve efficiency and speed of computer data managing and communications,and improve system＇s integer and reduce system＇s error.