基于FPGA的积分型数字锁相环的设计与实现

Design and Implementation of Integral DPLL Based on FPGA

位同步时钟信号的提取是通信系统中的关键部分,应用数字锁相环可以准确地从输入码流中提取出位同步信号。本文简要介绍了数字锁相环的基本原理,在详细介绍了积分型超前—滞后数字锁相环的工作原理的基础上,利用VHDL语言对该系统进行了设计,给出了数字锁相环路主要模块的设计方法及仿真结果,得到了该系统的顶层电路,其中重点分析了积分型数字鉴相器的原理,给出了设计过程;并根据系统的参数进行了性能分析,最后给出了整个系统的功能仿真结果。具有一定的工程实用价值。

Bit synchronous clock recover circuit is the key part of the communication system, it can exactly recover the synchronous signal from input data stream. This paper gives a brief introduction to the principle of Digital Phase Locked Loop （DPLL） ,and uses VHDL language to design this system based on the principle of integral lead-lag DPLL,and presents the design method and simulation result of the main modules,and then gets the top circuit. The emphases of this paper are the principle of integral digital phase detector and design process. Finally based on the parameter it gives the performance analyzing. The system has applicable importance in practicing.