可纠正单个错误的并行CRC解码器的设计

Design a Parallel CRC Decoder with Single Bit Error Correction

在数据传输的过程中通常使用循环冗余校验(CRC),以检查数据传送过程中是否发生了错误。通常当解码器发现数据帧中有错误发生时都会要求重新发送该数据帧。针对有的同步协议要求解码器同时具有纠正帧头部分发生的单个错误的功能。以CRC的基本原理为基础,分别从算法和程序实现上,介绍了一种高效的硬件实现并行8位CRC ITU T检查并纠正发生在16位原始数据和16位CRC码中单个传输错误的校验器。最后给出了相应的综合结果和时序仿真图。

Cyclic Redundancy Check （CRC） is often employed to detect errors incurred during transmission. When errors in data frame are detected by decoder,retransmission is often requested. But some synchronous communication protocols demand for single bit error correction capabilities for the header part of the frame. Based on the theoretical analysis of principle of CRC,the algorithm and how to program are discussed ,this paper introduces an efficient hardware 8 b parallel CRC-ITU-T decoder which can detect multiple bit error and correct single bit transport error in 16 b of original data or in 16 b of CRC code. At last it shows the results of synthesis and timing simulation diagram.