高速科学CCD CAMERA系统设计

System design of high-speed science-grade CCD camera

在实验结果的基础上,介绍了一种高速科学CCD相机系统设计。测试选用了柯达CCD芯片KAF-0401LE和KAF-1001E,用MAXII系列CPLD芯片实现了CCD驱动时序和数据采集时序控制;采用片内集成CDS的CCD信号A/D转换器AD9824进行相关双采样和高速模数转换;内置8051的CypressUSB2.0控制芯片CY7C68013A完成了高速同步数据传输及与上位机通讯,接收和发送上位机指令等;结合USB采集系统使用VisualC++编写了系统控制界面。实现了采集速率选择(最高10MHzPixelRate对应于20Mbyte/sUSB传输速度)、复合模式选择、单帧/连续采集、制冷温度采集和控制等,适用于同类型CCD相机的系统设计。

A science-grade CCD has high quantum efficiency, low dark current, and extremely high full well capacity, and it is ideal for high dynamic range applications such as solar astronomy, radiology, and echelle spectroscopy.. This paper describes in detail a design course of high-speed CCD system. Featuring the Eastman Kodak Full-Frame CCD image sensor KAF-0401LE and KAF-1001E. CPLD of MAX II family, which contains the Clocking State Machine that controls the operational flow of the circuit, is used to generate system＇s timing clocks. The AD9824 chip is a complete analog signal processor for CCD application. Signal chain consists of an input clamp, a 30MSPS CDS, PxGA, VGA, and a 14-bit 30MSPS A/D Converter. It is used to simplify the circuit. The CY7C4285V chip is high-speed, First-In-First-Out （FIFO） memories. It provides solutions for a wide variety of data buffering, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. It can be used to make sure of no data missing in the high-speed data transmission. Another USB 2.0 microcontroller CY7C68013A chip affords data transmission and system controlling. The system realizes the functions such as pixel rate selection （Maximum 10MHz Pixel Rate equal 20Mbyte/s USB data transmission speed）, setting integration time, asymmetric binning mode selection, one frame/continuous frames, temperature collection and so on.