一种有效的多时钟网络时钟树综合方案

An Effective Clock Tree Synthesis Method for Multi-clocks Networks

时钟树综合在芯片设计后端物理设计过程中,对于保证数字集成电路的时序是非常重要的。针对设计中存在的分频时钟,在时钟树综合时,将源时钟和分频时钟放在同一个时钟树中,把分频时钟的时钟网络作为源时钟的子树,很好地解决了分频时钟和源时钟之间的时钟偏移,满足了同步时序要求。该方法用于实际设计项目中,取得了非常好的效果。

To ensure timing requirement on digital integrated circuits, clock tree synthesis is very important on ASIC backend physical layout design. This paper shows an effective clock tree synthesis method for divided clocks, when doing clock tree synthesis, putting source clock and divided clock in the same clock tree, treating divided clock network as a sub- tree of source clock tree, solves clock skew problem between divided clock and source clock very well, satisfies synchronous timing requirement. This method is used in our project and has a good effect.