摘要
以CPLD为主要硬件设计一个数字电压表,其功能由VHDL编程决定,实现了硬件设计软件化,使系统的灵活性显著提高.仿真及硬件测试表明:数字电压表能测量和显示0～5V电压,测量精度为0.02V.
A Digital Voltage Meter is Designed mainly with CPLD and its function can be decided flexiblely by VHDL program. Result from emulate and testing indicates the meter can measure voltage with a range from 0 to 5V and a resolving power 0.02V.
出处
《自动化与仪器仪表》
2005年第6期68-69,81,共3页
Automation & Instrumentation
