摘要
研究了以ZnO-Bi2O3-SiO2系为基础,适当添加Co、Mn、Sb、Cr、Ni等金属氧化物的叠层片式ZnO压敏电阻器配方。通过严格控制Bi2O3及SiO2的含量,较好地解决了瓷料与银鈀内电极的共烧问题,且电性能优良。其瓷料的特点是烧结温度低(<1050℃),产品非线性系数高(≥25),泄漏电流小(<5μA),限制电压低(V1A/V1mA<1.70),通流能量大(≥1800A/cm2)。
The formula of multilayer chip ZnO varistor, which has a composition containing ZnO-Bi2O3-SiO2 as a main component, and Co, Mn, Sb, Cr, Ni as additives was studied, The co-firing problem between ceramic material and silver/palladium was solved by strictly controlling the contents of Bi2O3 and SiO2. Obtained products have following advantages： low sintering temperature （〈1 050℃）, high nonlinear coefficient （≥25）, low leakage current （〈5 μA）, low clamping voltage （V1A/V1mg〈1.70） and excellent transient energy absorption （≥1 800 A/cm^2）.
出处
《电子元件与材料》
CAS
CSCD
北大核心
2005年第12期44-45,共2页
Electronic Components And Materials
