摘要
提出了一种适用于H.264标准中1/4精度像素插值算法的硬件实现架构。对于亮度分量,采用了一维处理单元(PE)阵列来实现1/4精度像素插值算法中的亮度半像素的插值,同时采用一个6×4的寄存器阵列转置已得到的半像素以进行下一步的亮度的1/4精度像素插值。而对于色度分量,笔者采用了一种只含移位和加法运算的插值核架构来实现色度的1/8像素插值。笔者提出的架构可在一定的时钟周期内,计算出不同位置上的插值像素,且有面积小,速度快的特点。
In this paper, a VLSI architecture for quarter-pixel interpolation in H,264 is proposed, As for the luminance component, a 1-D processing element （PE） array is adopted to implement half-pixel interpolation of luminance in quarter-pixel interpolation, in the meantime, the half pixel with a 6×4 register array is transposed in order to executing the next step of quarter-pixel interpolation in luminance. While for the chrominance component, we propose an interpolation core architecture that includes only shift and add operations to implement eighth-pixel interpolation in chrominance, The architecture that we propose can compute interpolating pixel at different places in a certain number of clock cycles, with less number of gates and faster sliced.
出处
《电视技术》
北大核心
2005年第10期14-17,共4页
Video Engineering
