一种SDA数字滤波器的低功耗设计

Low-Power Design of SDA Digital Filter

SDA(Seria l D istribu ted A rithm etic,SDA)数字滤波器具有速度快、结构规整等优点,广泛应用于数字信号处理器芯片级电路实现中.SDA在采样数据值位跳变频率比较高时,会导致很大的移位寄存器功耗,降低了SDA的性能、功耗比.研究SDA数字滤波器的低功耗设计,主要途径是通过一种优化阶符的二进制数据表示方式来表示采样数据,以达到减小采样数据值位跳变频率的目的,从而实现减小SDA数字滤波器的功耗.实验结果表明,本文研究的低功耗设计方法可有效减小SDA数字滤波器10%的功耗.

SDA （Serial Distributed Arithmetic,SDA） digital filter is widely used by DSP chip designer , because it has a fast speed and regular structure. Unfortunately, SDA will give rise to high power dissipation when the sampled data have a high bit reverse frequency. In order to reduce the effect of this phenomenon, our strategy is to use a new data coding technique to express the sampled data, which is called optimized radix-notation binary coding method. The verification experiment shows that optimized radix-notation binary coding method can reduce SDA digital filter power dissipation 10 percent.