一种SOC原型机的建立与IP模块验证

Building of SOC Prototype Machine and IP Modules Verification

SOC(System On Ch ip)将原来分立器件实现的CPUs、DSPs和存储器等模块整合在一个单芯片内,这种设计方法使得外围的IP模块的复用变得非常重要。而复用的IP模块必须嵌入到SOC中进行系统验证后才能使用,系统功能验证通常使用原型机的验证方法。该文论述了汉芯SOC的FPGA原型机验证环境的实现方法,以及如何使用串口建立起PC机与原型机的通讯。原型机验证中的一个普遍问题是ASIC设计代码不能直接映射到FPGA,否则会造成FPGA实现的硬件效率低,甚至时序不能满足从而导致验证失败,该文以门控时钟为例,对这种代码的转换提出一种可行的方法,并对转换前后的性能做了对比。最后,以一个常用的IP模块为例,对复用IP模块的系统原型机实时验证进行技术研究与探讨。

Nowadays many modules, such as CPUs, DSPs and Memory, which were implemented by isolated components in all of previous circuit design ,could be merged into a single chip, but in this approach it is very important to reuse the peripheral IP modules. The IP modules could be reused after system verification which makes use of prototype machine usually. A FPGA prototype machine was built for Hisys SOC＇ s system verification. And in this prototype verification environment, the program developed for this SOC verification could be download through UART form PC to the FPGA board. ASIC RTL code can not be wholly mapped into FPGA without any modification, otherwise this FPGA prototype machine would be low performance and the timing requirement could not be met. This paper studies the ASIC - TO - FPGA RTL code transformation and an efficient approach is presented. At last, as an example of IP reuse, the Nand Flash Controller module verification was mentioned.