期刊文献+

基于MEDICI仿真的ESD保护器件设计方法 被引量:2

An ESD Protection Device Simulation-Design Methodology by Using MEDICI
下载PDF
导出
摘要 文章讨论了用MEDICI作基于仿真的ESD保护电路设计方法,并以GGNMOS为例,给出了MEDICI仿真结果与实验数据的对照。结果表明此方法是一种有效仿真ESD保护电路在高温高电压大电流下特性的方法,可使ESD保护器件的设计周期缩短,成功率因此大大增加。 In this paper, an ESD protection circuit simulation-design methodology based on MEDICI was discussed. With a GGNMOS as an example, the simulation results were analyzed as compared to the experimental results. And it is testified that this methodology is effective in simulating the ESD performance of the protection device under high temperature and high current conditions. Hence, the design cycle is greatly reduced and the possibility of tape-out success is improved.
出处 《微电子学与计算机》 CSCD 北大核心 2005年第12期70-73,77,共5页 Microelectronics & Computer
基金 国家"十五"预研基金项目(41308060602) 电子元器可靠件物理及其应用技术国家级重点实验室基金资助
关键词 ESD GGNMOS MEDICI 器件仿真 ESD, GGNMOS, MEDICI, Device simulation
  • 相关文献

参考文献9

  • 1G Boselli, A J Mouthaan, F G Kuper. Device Simulation of ESD Events in Protection Structures. ICSDT 1998.
  • 2Yoon J Huh, Valery Axerad, Jau Wen Chen, Peter Bendix.The Effect of Substrate Coupling on Triggering Uniformity and ESD Failure Threshold of Fully Silicided NMOS Transistors. Symposium on VLSI Technology Digest of Technical, 2002: 220~221.
  • 3MEDICI 2D Semiconduc Tor Device Simulation User's Manual, Avant! Corp.
  • 4Ajith Amerasekera, Charvaka Duvvury. ESD in Silicon Integrated Circuits, John Wiley & Sons, 2002: 335~341.
  • 56S06DPDM - CT02 Process Outline. Wuxi CSMC - HJ Semiconductor Co., Ltd.
  • 66S06DPDM - CT02 Process Electrical Design Rule. Wuxi CSMC-HJ Semiconductor Co., Ltd.
  • 70.6um DPDM Mixed Signal Technology Topological Design Rule. Wuxi CSMC-HJ Semiconductor Co., Ltd.
  • 8罗宏伟,师谦.集成电路抗ESD设计中的TLP测试技术[J].电子产品可靠性与环境试验,2003,21(4):44-46. 被引量:13
  • 9Kwang Hoon Oh, Charvaka Duvvury, et al. Investigation of Gate to Contact Spacing Effect on ESD Robustness of Salicided Deep submicron Single finger NMOS Transistors.IEEE 02CH37320, 40th Annual International Reliability Physics Symposium, Dallas, Texas, 2002: 148~155.

二级参考文献5

  • 1Maloney T J, Khurana N. Transmission Line Pulsing Techniques for Circuit Modeling of ESD Phenomena[A]. 7 th EOS/ESD Symposium[C]. 1985. 49 - 54.
  • 2Voldman S, Gauthier R, Morrisseau K, et al . High- Current Characterization of Dual -Damascene Copper Interconnects in SiO2-and Low- k Interlevel Dielectrics for Advanced CMOS Semiconductor Technologies[A]. IEEE IRPS[C]. 1999. 144-153.
  • 3Chen T P, Chan R. Reproducibility of Transmission Line Measurement of Bipolar I- V Characteristics of MOSFET' S[J]. IEEE Trans. On Instrumentation and Measurement,1999,48(3): 721-723.
  • 4Meneghesso G, Santirosi S, Novarini E, et al. ESD robustness of smart -power protection structures evaluated by means of HBM and TLP tests[A]. IEEE IRiS[C]. 2000.270 - 275.
  • 5Lee J C, Hoque M A, Croft G D, et al. A Method for Determining a Transmission Line Pulse Shape That Produces Equivalent Results to Human Body Model Testing Methods[A]. EOS/ESD Symposium Proceedings[C]. 2000. 97-103.

共引文献12

同被引文献8

  • 1刘丰.ColdFire微控制器芯片ESD/EFT保护技术研究[D/R].天津:天津大学,2010:37-39.
  • 2Huang,J.B,G.W.Wang.ESD protection design for advanced CMOS[C].Advances in Microelectronic Device Technology.Bellingham USA:SPIE,2002:123-132.
  • 3苏庆.研究在深亚微米技术下ESD防护策略[D/R].上海:复旦大学,2007:24-25.
  • 4synopsys公司.Sentaurus Device User Guide Version D-2010.03[pdf].California,USA:synopsys Co.,2010:910-952.
  • 5Bock K,Keppen B,Heyn B.Influence of gate length on ESD performancefor deep sub-micron CMOS technology[C].Microelectronics Reliability.Orlando,USA,2001:375-383.
  • 6薛婧,肖立伊,曾名志.深亚微米ESD保护器件GGNMOS性能分析与设计[J].中国集成电路,2007,16(12):46-50. 被引量:2
  • 7于宗光.CMOS集成电路的ESD设计技术[J].电子产品可靠性与环境试验,2001,19(2):16-21. 被引量:9
  • 8薛忠杰.CMOS VLSI ESD保护电路设计技术[J].微电子技术,1999,27(2):46-51. 被引量:5

引证文献2

二级引证文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部