摘要
随着微处理器运算速度的大幅度提高,对快速加法器的需求也越来越高。当VLSI工艺进入深亚微米阶段的时候,很多情况下,无论是在面积还是在时序上连线都起着决定性的作用。文章基于不同的CMOS工艺,针对三种不同结构的并行前缀加法器,在不同数据宽度的情况下进行性能比较,根据深亚微米下金属互连线对加法器性能的影响,挑选出适合深亚微米工艺的加法器结构。
With the great increase of the speed of modern microprocessors, the need of fast adders becomes more exigent. When the technology has got the stage of deep submicron, the connective wire will play an important role either in the area or in the timing. Based on various CMOS technologies： 0.18μm, 0.15μm, 0.13μm and 90nm, this thesis makes a performance comparison with different bit widths, and then selects the adder architecture fit for deep submicron technology according to the impact of connective wires on adder performance in deep submicron technology.
出处
《微电子学与计算机》
CSCD
北大核心
2005年第12期92-95,共4页
Microelectronics & Computer
基金
国防"十五"预研课题(41308010108)
西北工业大学研究生创业种子基金(Z20040050)
