通用异步串行接口的VHDL实用化设计

Practical Design of UART based on VHDL

通用异步串行接口(UniversalAsynchronousReceiverTransmitter,UART)在通信、控制等领域得到了广泛应用。根据UART接口特点和应用需求,以提高VHDL设计的稳定性和降低功耗为目标,本文讨论了UART接口中时钟域划分、时钟分频、亚稳态、同步FIFO设计等问题和解决方案。

UART is widely used, especially in communication and control system. In this paper, considering characters of UART and requests of the real implements, some questions and their solutions such as clock distribution, frequency divider, metastability, Synchronous FIFO are discussed, aiming at improving the robustness and reducing power consumption of the UART design based on VHDL.