CMOS数字锁相环中的自校准技术

Self-Calibration Technique for CMOS Digital Phase Locked Loop

提出了一种数字锁相环(DPLL).该电路采用自校准技术,具有快速锁定、低抖动、锁定频率范围宽等优点.设计的锁相环在1.8 V外加电源电压时,工作在60～600 MHz宽的频率范围内.电路采用5层金属布线的0.18 μm CMOS工艺制作.测试结果显示,电路的峰-峰抖动小于输出信号周期(Tout)的0.5%,锁相环锁定时间小于参考时钟预分频后信号周期(Tpre)的150倍.

A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire fast locking, low jitter, and a wide locking range. The DPLL operates from 60 MHz to 600 MHz at a supply voltage of 1.8 V, and it has been implemented in a 0.18μm quintuplemetal CMOS process. The peak-to-peak jitter of the circuit is less than 0.5% of the output period, Tout, and the locking time is less than 150 times of the reference clock period after prescaler, Tpre.