一种适用于NRZ数据的时钟数据恢复电路

A Clock and Data Recovery Circuit for Non-Return-Zero Data

提出了一种基于传统电荷泵锁相环结构的时钟数据恢复电路。采用一种适用于NRZ数据的新型鉴频鉴相器电路,以克服传统鉴频鉴相器在恢复NRZ信号时出现错误脉冲的问题,从而准确地恢复出NRZ数据。同时,对其他电路也采用优化的结构,以提高时钟数据恢复电路的性能。设计的电路可在1.1 V超低电压下工作,适合RF ID等需要低电压、低功耗的系统使用。

A clock and data recovery （CDR） circuit for non-return-zero （NRZ） data is presented, which is based on conventional charge-pump phase-locked loop （CP PLL）. A new phase/frequency detector （PFD） is proposed for the CDR circuit to solve the problem of error pulse when dealing with NRZ data. With the new PFD, the CDR circuit can recover NRZ data accurately. Other circuits of the CDR are also optimized, in order to achieve a high performance. Capable of operating at 1.1 V supply voltage, the CDR circuit is suitable for low voltage and low power applications, such as RF ID systems.