8B/10B编码器的设计及实现

Design and Realization of an 8B/10B Encoder

本文介绍了8B/10B编码技术,提出了一种简单、实用的8B/10B编码器的实现方法,并且采用Verilog语言设计了一种通用的软核。通过在FPGA器件上进行测试,电路稳定、可靠,可直接嵌入到需要8B/10B编码功能的收发器电路中。

This paper introduces 8 B/10B encoding technique, and puts forward a simple and practical realization method of an 8B/10B encoder. Furthermore, a versatile soft -core designed with Verilog is presented. It is tested to be stable and reliable by FPGA devices, and can be directly embedded in transceiver circuit with 8B/10B encoding function.